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Low Bit Rate Voiceband Encoders/Decoder
Semiconductor
February 1999
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HC-55564
Continuously Variable Slope Delta-Modulator (CVSD)
Features
* All Digital
Description
The HC-55564 is a half duplex modulator/demodulator CMOS intergrated circuit used to convert voice signals into serial NRZ digital data and to reconvert that data into voice. The conversion is by delta-modulation, using the Continuously Variable Slope (CVSD) method of modulation/demodulation. While the signals are compatible with other CVSD circuits, the internal design is unique. The analog loop filters have been replaced by very low power digital filters which require no external timing components. This approach allows inclusion of many desirable features which would be difficult to implement using other approaches. The fundamental advantages of delta-modulation, along with its simplicity and serial data format, provide an efficient (low data rate/low memory requirements) method for voice digitization. The HC-55564 is usable from 9kbits/s to above 64kbps. See the Harris Military databook for a MIL-STD-883C compliant CVSD. Application Note 607.
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* Requires Few External Parts * Low Power Drain: 1.5mW Typical From Single 4.5V To 6V Supply * Time Constants Determined by Clock Frequency; No Calibration or Drift Problems: Automatic Offset Adjustment * Half Duplex Operation Under Digital Control * Filter Reset Under Digital Control * Automatic Overload Recovery * Automatic "Quiet" Pattern Generation * AGC Control Signal Available
Applications
* Voice Transmission Over Data Channels (Modems) * Voice/Data Multiplexing (Pair Gain) * Voice Encryption/Scrambling * Voicemail * Audio Manipulations: Delay Lines, Time Compression, Echo Generation/Suppression, Special Effects, etc. * Pagers/Satellites * Data Acquisition Systems * Voice I/O for Digital Systems and Speech Synthesis Requiring Small Size, Low Weight, and Ease of Reprogrammability * Related Literature - AN607, Delta Modulation for Voice Transmission
Ordering Information
PART NUMBER HC1-55564-2 HC1-55564-5 HC1-55564-9 HC3-55564-5 HC9P55564-5 TEMP. RANGE (oC) -55 to 125 0 to 75 -40 to 85 0 to 75 0 to 75 PACKAGE 14 Ld CERDIP 14 Ld CERDIP 14 Ld CERDIP 14 Ld PDIP PKG. NO. F14.3 F14.3 F14.3 E14.3
16 Ld Plastic SOIC (W) M16.3
Pinouts
HC-55564 (PDIP, CERDIP) TOP VIEW HC-55564 (SOIC) TOP VIEW
VDD
1
14 DIG OUT 13 FZ 12 DIG IN 11 APT 10 ENC/DEC 9 CLOCK 8 DIG GND
VDD
1
16 DIG OUT 15 FZ 14 DIG IN 13 APT 12 ENC/DEC 11 CLOCK 10 DIG GND 9 NC
ANALOG GND 2 AOUT 3
ANALOG GND 2 AOUT 3
AGC 4 AIN 5 NC 6 NC 7 NC 8
AGC 4 AIN 5
NC 6 NC 7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) Harris Corporation 1999
File Number
2889.5
1
HC-55564
Absolute Maximum Ratings
Voltage at Any Pin . . . . . . . . . . . . . . . . . . . .GND -0.3V to VDD 0.3V Maximum VDD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range HC-55564-5, -7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 750C HC-55564-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 850C HC-55564-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 1250C Operating VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 6.0V
Die Characteristics
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1897 Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 x 82 Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VDD Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BiMOSE
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Sampling Rate Supply Current Logic `1' Input Logic `0' Input Logic `1' Output Logic `0' Output Clock Duty Cycle Audio Input Voltage Audio Output Voltage Audio Input Impedance Audio Output Impedance Transfer Gain Syllabic Filter Time Constant Signal Estimate Filter Time Constant Enc Threshold Minimum Step Size Quieting Pattern Amplitude AGC Threshold Clamping Threshold
Unless Otherwise Specified, typical parameters are at 25oC, Min-Max are over operating temperature ranges. VDD = 5.0V, Sampling Rate = 16Kbps, AG = DG = 0V, AIN = 1.2VRMS SYMBOL CLK IDD VIH VIL VOH VOL AIN AOUT ZIN ZOUT AE-D tSF tSE Note 3 Note 3 Note 4 Note 4 AC Coupled (Note 5) AC Coupled (Note 6) Note 7 Note 7 No Load, Audio In to Audio Out. Note 8 Note 8 AIN at 100Hz (Note 9), (Typ) 0.3% = 15mVRMS MSS VQP VATH VCTH Note 10 FZ = 0V or APT = 0V (Note 11) Note 12 Note 13 Note 2 CONDITIONS MIN 9 3.5 4.0 30 -2.0 1.0 TYP 16 0.3 0.5 0.5 280 150 4.0 6 0.1 10 0.1 0.75 MAX 64 1.5 1.5 0.4 70 1.2 1.2 +2.0 UNITS kbps mA V V V V % VRMS VRMS k k dB ms ms mVPEAK %VDD mVP-P F.S. F.S.
NOTES: 2. There is one NRZ (Non-Return Zero) data bit per clock period. Data is clocked out on the negative clock edge. Data is clocked into the CVSD on the positive going edge (see Figure 2). Clock may be run at less than 9kbps and greater than 64kbps. 3. Logic inputs are CMOS compatible at supply voltage and are diode protected. Digital data input is NRZ at clock rate. 4. Logic outputs are CMOS compatible at supply voltage and will withstand short-circuits to VDD or ground. Digital data output is NRZ and changes with negative clock transitions. Each output will drive one LS TTL load. 5. Recommended voice input range for best voice performance. Should be externally AC coupled. 6. May be used for side-tone in encode mode. Should be externally AC coupled. Varies with audio input level by 2dB. 7. Presents series impedance with audio signal. Zero signal reference is approximately VDD/2. 8. Note that filter time constants are inversely proportional to clock rate. Both filters approximate single pole responses. 9. The minimum audio input voltage above which encoding takes place. 10. The minimum audio output voltage change that can be produced by the internal DAC. 11. Settled value, the "quieting" pattern or idle-channel audio output steps at one-half the bit rate, changing state on negative clock transitions. 12. A logic "0" will appear at the AGC output pin when the recovered signal reaches one-half of full-scale value (positive or negative), i.e., at VDD/2 25% of VDD. 13. The recovered signal will be clamped, and the computation will be inhibited, when the recovered signal reaches three-quarters of fullscale value, and will unclamp when it falls below this value (positive or negative).
2
HC-55564 Pin Descriptions
PIN NUMBER 14 LEAD DIP 1 2 3 SYMBOL VDD Analog GND AOUT DESCRIPTION Positive Supply Voltage. Voltage range is 4.5V to 6.0V. Analog Ground connection to D/A ladders and comparator. Audio Out recovered from 10-bit DAC. May be used as side tone at the transmitter. Presents approximately 150k source with DC offset of VDD/2. Within 2dB of Audio Input. Should be externally AC coupled. Automatic Gain Control output. A logic low level will appear at this output when the recovered signal excursion reaches one-half of full scale value. In each half cycle full scale is VDD /2. The mark-space ratio is proportional to the average signal level. Audio Input to comparator. Should be externally AC coupled. Presents approximately 280k in series with VDD/2. No internal connection is made to these pins. Logic ground. 0V reference for all logic inputs and outputs. Sampling rate clock. In the decode mode, must be synchronized with the digital input data such that the data is valid at the positive clock transition. In the encode mode, the digital data is clocked out on the negative going clock transition. The clock rate equals the data rate. A single CVSD can provide half-duplex operation. The encode or decode function is selected by the logic level applied to this input. A low level selects the encode mode, a high level the decode mode. Alternate Plain Text input. Activating this input caused a digital quieting pattern to be transmitted, however; internally the CVSD is still functional and a signal is still available at the AOUT port. Active low. Input for the received digital NRZ data. Force Zero input. Activating this input resets the internal logic and forces the digital output and the recovered audio output into the "quieting" condition. An alternating 1-0 pattern appears at the digital output at 1/2 the clock rate. When this is decoded by a receive CVSD, a 10mVP-P inaudible signal appears at audio output. Active low. Output for transmitted digital NRZ data.
4
AGC
5 6, 7 8 9
AIN NC Digital GND Clock
10 11 12 13
Encode/ Decode APT Digital In FZ
14 NOTE:
Digital Out
14. No active input should be left in a "floating condition."
Functional Diagram
(1) VDD
(DIP Pin Numbers Shown)
(12) DIGITAL IN VDD 2 (10) ENC/DEC (9) CLOCK (8)
(11) (13) FORCE APT ZERO RESET T D
DIGITAL GND (14) DIGITAL OUT
3V TO 6V
F/F
Q
(5) AIN ZIN (2) ANALOG GND COMPARATOR
3 BIT SHIFT REGISTER
10 BIT DAC 10 10 RESET
STEP SIZE LOGIC
(3) AOUT (SIDE TONE) ZOUT (4) AGC OUT
SIGNAL ESTIMATE FILTER 1msec
6
DIGITAL MODULATOR 1
SYLLABIC FILTER 4ms
10 BIT DAC RESET
3
HC-55564 Timing Waveforms
SAMPLING CLOCK
FZ/APT
DEC/ENC
DIGITAL NRZ IN tDS DIGITAL NRZ OUT
1
0
1
0 tDS: DATA SET UP TIME 100ns TYPICAL
0
1
1
FIGURE 2. CVSD TIMING DIAGRAM
Interface Circuit for HC-55564 CVSD
AUDIO SOURCE TP3040 INPUT LEVEL ADJUST RA, RB, CA OPTIONAL CA RA 5V -5V RC 1 2 3 4 RB 5 9 8 VFX1+ VFX1GSX VFR0 PWRI VCC VBB GNDA 0.1 0.1 15 CLK 12 CLK0 PDN GNDD PWR0+ VFX0 VFRI
(DIP Pin Numbers Shown)
HC-55564 6 16 10 0.1 0.1 RD (NOTE) 1 14 13 11 EXTERNAL CONTROL 0.1 8 AUDIO OUT 5 3 AIN AOUT 4 AGC DOUT DIN FZ VDD APT E/D 14 12 13 11 10 EXTERNAL CONTROL (TO DATA I/F) (FROM DATA I/F)
DIGITAL ANALOG GND GND CLK 9
2
/n
CLK GEN
NOTE: RD = 100k to 1M
only to Pin 2. CVSD Hookup for Evaluation The circuit in Figure 3 is sufficient to evaluate the voice quality of the CVSD, since when encoding, the feedback signal at the audio output pin is the reconstructed audio input signal. CVSD design considerations are as follows: 1. Care should be taken in layout to maintain isolation between analog and digital signal paths for proper noise consideration. 2. Power supply decoupling is necessary as close to the device as possible. A 0.1F should be sufficient. 3. Ground, then power, must be present before any input signals are applied to the CVSD. Failure to observe this may cause a latchup condition which may be destructive. Latchup may be removed by cycling the power off/on. A power-up reset circuit may be used that strobes Force Zero (Pin 13) during power-up as follows: 4. Analog (signal) ground (Pin 2) should be externally tied to Digital GND (Pin 8) and power supply ground. It is recommended that the AIN and AOUT ground returns connect 5. Digital inputs and outputs are compatible with standard CMOS logic using the same supply voltage. All unused logic inputs must be tied to the appropriate logic level for desired operation. It is recommended that unused inputs tied high be done so through a pull-up resistor (1k to 10k). TTL outputs will require 1k pull-up resistors. Pins 4 and 14 will each drive CMOS logic or one low power TTL input. 6. Since the Audio Out pins are internally DC biased to VDD/2, AC coupling is required. In general, a value of 0.1F is sufficient for AC coupling of the CVSD audio pins to a filter circuit. 7. The AGC output may be externally integrated to drive an AGC pre-amp, or it could drive an LED indicator through a buffer to indicate proper speaking volume.
VDD
R (13) C FZ
4
HC-55564
Figures 4, 5, and 6 illustrate the typical frequency response of the HC-55564 for varying input levels and for varying sampling rates. To prevent slope overload (slew limiting), the 0dB boundary should not be exceeded. The frequency response is directly proportional to the sampling clock rate. The flat bandwidth at 0dB doubles for every doubling in sampling rate. The output levels were measured in the encode mode, without filtering, from AIN to AOUT, at VDD = 5V. 0dB = 1.2VRMS.
AOUT AIN
0dB = INPUT SIGNAL LEVEL -6dB -12dB -20 -24dB -30dB -36dB -40 dB -30 1000 INPUT FREQUENCY AT AIN (Hz) 10000 -18dB -10
100
FIGURE 4. 16kbps
AOUT AIN
0dB = INPUT SIGNAL LEVEL -6dB -12dB dB -30 -40 1000 INPUT FREQUENCY AT AIN (Hz) 10000 -18dB -24dB -30dB -36dB -20 -10
100
FIGURE 5. 32kbps
AOUT AIN
0dB = INPUT SIGNAL LEVEL -6dB -12dB -20 dB -30 -40 1000 INPUT FREQUENCY AT AIN (Hz) 10000 -18dB -24dB -30dB -36dB -10
100
FIGURE 6. 64kbps
5
HC-55564
The following typical performance distortion graphs were realized with the test configuration of Figure 7. The measurement vehicle for Total Harmonic Distortion (THD) was an HP-339A distortion measurement set, and for 2nd
0.33F 5 FUNCT. GEN. 1 HC-55564 AIN AOUT 0.33F 3 HP3582A SPECTRUM ANALYZER OR HP339A DISTORTION ANALYZER
and 3rd harmonic distortion, an HP-3582A spectrum analyzer. All measurement conditions were at VDD = 5V, and 2nd and 3rd harmonic distortion measurements were Cmessage filtered. 0dB = 1.2VRMS.
C-MESSAGE FILTER
-10 16KHz -20 THD (dB) -30 -40 -24 32KHz 64KHz INPUT FREQ. = 1kHz
30% 10% 3% 1% -16 -8 0 INPUT SIGNAL LEVEL (dB)
DEC/ 10 ENC 11 8 APT DGND 13 2 FZ AGND VDD
5V
+1.0F
FIGURE 7. TEST AND MEASUREMENT CIRCUIT
FIGURE 8. CVSD SIGNAL LEVEL vs TOTAL HARMONIC DISTORTION
CVSD SIGNAL TO 2ND AND 3RD HARMONIC DISTORTION C-MESSAGE WEIGHTED -10 VIN = 0.5VRMS 16kHz CLOCK 3RD
CVSD INPUT LEVEL vs 2ND AND 3RD HARMONIC DISTORTION C-MESSAGE WEIGHTED -10 INPUT -20 FREQUENCY 1kHz dB -30 -40 -50 -24 16kHz CLOCK 3RD 2ND dB -20 -30 -40 -17 -11 -3.8 +3.0 -50
2ND 0 1000 2000 3000
INPUT SIGNAL LEVEL (dB)
INPUT FREQUENCY (Hz)
FIGURE 9A.
CVSD INPUT LEVEL vs 2ND AND 3RD HARMONIC DISTORTION C-MESSAGE WEIGHTED -10 -20 dB -30 -40 -50 -24 2ND -10 INPUT FREQUENCY 1kHz 32kHz CLOCK dB 3RD -20 -30 -40 -50 -60 -17 -11 -3.8 +3.0 0 1000
FIGURE 10A.
CVSD SIGNAL TO 2ND AND 3RD HARMONIC DISTORTION C-MESSAGE WEIGHTED VIN = 0.5VRMS 32kHz CLOCK
2ND 3RD 2000 INPUT FREQUENCY (Hz) 3000 4000
INPUT SIGNAL LEVEL (dB)
FIGURE 9B.
CVSD INPUT LEVEL vs 2ND AND 3RD HARMONIC DISTORTION C-MESSAGE WEIGHTED -10 INPUT -20 dB -30 -40 3RD -50 -24 -17 -11 -3.8 +3.0 FREQUENCY 1kHz 2ND dB -30 -40 -50 64kHz CLOCK -10 -20
FIGURE 10B.
CVSD SIGNAL TO 2ND AND 3RD HARMONIC DISTORTION C-MESSAGE WEIGHTED VIN = 0.5VRMS 64kHz CLOCK
2ND 3RD
-60 0 1000 2000 INPUT FREQUENCY (Hz) 3000 4000 INPUT SIGNAL LEVEL (dB)
FIGURE 9C. FIGURE 9. CVSD INPUT LEVEL vs 2ND AND 3RD HARMONIC DISTORTION
FIGURE 10C. FIGURE 10. CVSD INPUT FREQUENCY vs 2ND AND 3RD HARMONIC DISTORTION
6
HC-55564 Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.785 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 19.94 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
c1 D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 14 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 14 5.08 1.52 105o 0.38 0.76 0.25 0.038
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
aaa bbb ccc M N
7
HC-55564 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E14.3 (JEDEC MS-001-AA ISSUE D)
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E
A A1 A2 B B1 C D D1 E
-C-
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm).
E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 14 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 14
2.93
8
HC-55564 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA hx 45o H 0.25(0.010) M BM
M16.3 (JEDEC MS-013-AA ISSUE C) 16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A A1
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 10.10 7.40 MAX 2.65 0.30 0.51 0.32 10.50 7.60 NOTES 9 3 4 5 6 7 8
o
MIN 0.0926 0.0040 0.013 0.0091 0.3977 0.2914
MAX 0.1043 0.0118 0.0200 0.0125 0.4133 0.2992
B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.394 0.010 0.016 16 0
o
1.27 BSC 10.00 0.25 0.40 16
o
e
B 0.25(0.010) M C AM BS
0.419 0.029 0.050
o
10.65 0.75 1.27
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
8
0
Rev. 0 12/93
9

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